Anritsu MP1777A Especificaciones descargar pdf (Pagina 8)

DIGITAL LINK MEASURING INSTRUMENTS

136 For product ordering information, see pages 4 –10

GPIB

For R&D of High-Speed Logic, ICS, Optical Modules and Devices

The MP1764C is used in combination with the MP

1763C Pulse Pattern

Generator to detect errors used to evaluate conformity with ITU-T

standards. In addition, complicated searching for input thresholds or

phase adjustments is simplified with the touch of a single key. These

functions are ideally suited for the research and development of ul-

trahigh-speed logic ICs and digital communication systems.

MX176400A Q and Eye Analysis Software controls MP1764C and

MP1763C from the PC to measure Q factor, eye margin, and eye dia-

gram. MX176401A SDH/SONET Pattern Editor controls the MP1764C

and MP1763C to generate frame pattern conforming to SDH/SONET

standards.

ERROR DETECTOR

MP1764C

12.5 GHz

Specifications

Continued on next page

Features

•

Auto-search function for setting optimum values of input threshold

and phase setting by a “one-touch” operation

•

Synchronization of 8 Mbits pattern is easily made within a short pe-

riod of time (when in frame mode)

•

Errors are detected in intervals as short as 0.1 sec.

•

Zero wait time counter gate

Operation frequency 0.05 to 12.5 GHz

Input waveform NRZ

Input amplitude 0.25 to 2.0 Vp-p

Threshold voltage variable range

–3.000 to +1.875 Vp-p (1 mV steps)

Data input Phase margin ≥70 ps (typical value at 10 Gb/s, PRBS 2

– 1, and an input amplitude of 1 Vp-p)

Input sensitivity 50 mVp-p (typical value at 10 Gb/s and PRBS 2

– 1

Termination Connected to GND or –2 V via a 50 Ω termination

Connector APC-3.5

Input waveform Rectangular wave (<0.5 GHz), rectangular or sine wave (≥0.5 GHz), duty factor: 50%

Input voltage 0.25 to 2.0 Vp-p

Clock

Input delay variable range ±500 ps (1 ps steps)

input

Polarity inversion CLOCK/CLOCK inversion possible

Termination Connected to GND or –2 V via a 50 Ω termination

Connector APC-3.5

Auto search function Provided

Pseudorandom binary

Pattern: 2

– 1 (n: 7, 9, 11, 15, 20, 23, 31)

sequence pattern (PRBS)

Mark ratio: 1/2, 1/4, 1/8, 0/8 (1/2, 3/4, 7/8, 8/8 are possible with logic inversion.)

Receive

Number of AND bit shift at mark ratio setting: 1, 3 bits (selectable by using DIP switch on rear panel)

pattern Data pattern Data length: 2 to 8388608 bits

Alternate pattern A/B pattern word length: 128 to 4194304 bits (128 bits steps), Number of loops: Controlled using external signal

Zero substitution pattern Zero bit length: 1 to (pattern length –1) bits, Pattern length: 2

(n: 7, 9, 11, 15)

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 65 66

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