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DIGITAL LINK MEASURING INSTRUMENTS

GPIB

For R&D of High-Speed Logic, ICs, Optical Modules and Devices

The MP1763C is used in combination with the MP1764C

Error Detector.

The amplitude of the clock and data signals can be varied from 0.25

to 2 Vp-p while the offset can be adjusted to within ±2 V so that the

amplitude and the offset margin can be measured. The clock has a

variable delay function so that time-dependent characteristics or

phase margins of the input clock and data can be measured. An M

series pseudorandom pattern representative of actual conditions or

a programmable pattern can be selected as cell data.

In addition, a 3.5 inch floppy disk drive is built in for storing preset data,

enabling rapid measurements to be performed by simply pressing a

key. A GPIB function is provided, enabling automatic or remote mea-

surement via an external controller.

The MP1763C is a pulse pattern generator ideal for research and de-

velopment of high-speed logic, ICs, and digital systems.

MX176400A Q and Eye Analysis Software controls MP1763C and

MP1764C from the PC to measure Q factor, eye margin, and eye dia-

gram. MX176401A SDH/SONET Pattern Editor controls the MP1763C

and MP1764C to generate frame pattern conforming to SDH/SONET

standards.

Features

•

High quality waveform

•

Low FM/PM-noise clock generator

•

8 Mbit programmable pattern corresponding to six frames of STM-

64/STS-192

•

Generates PRBS patterns with bit length from 2

– 1 to 2

–1

bits

•

Complementary outputs of both data and clock

•

The amplitudes and offsets of all 8 data outputs that have 1/8

speed of fundamental clock signal can be set

PULSE PATTERN GENERATOR

MP1763C

12.5 GHz

Specifications

•

MP1763C (main frame)

Continued on next page

Operation frequency 0.05 to 12.5 GHz

Frequency range 0.05 to 12.5 GHz

SSB phase noise (at 10 kHz ≤–85 dBc/Hz (0.05 to 4 GHz), ≤–80 dBc/Hz (4 to 8 GHz), ≤–75 dBc/Hz (8 to 10 GHz),

offset, 1 Hz bandwidth) ≤–70 dBc/Hz (10 to 12.5 GHz)

External clock input level 0.4 to 2.5 Vp-p

Pseudorandom binary

Pattern: 2

– 1 (n: 7, 9, 11, 15, 20, 23, 31)

sequence pattern (PRBS)

Mark ratio: 1/2, 1/4, 1/8, 0/8 (1/2, 3/4, 7/8, 8/8 are possible with logic inversion)

Bit shifts number for mark ratio varied: 1, 3 bits selectable

Data pattern Data length: 2 to 8388608 bits

Pattern

Alternate pattern A/B pattern data length: 128 to 4194304 bits (128 bit steps); Loop time: A, B pattern (1 to 127, 1 steps)

Zero substitution pattern Zero bit length: 1 to (pattern length – 1) bits; Pattern: 2

(n: 7, 9, 11, 15)

Error rate: 10

–n

(n: 4, 5, 6, 7, 8, 9), and single error

Error addition

External error injection: Provided

Internal

clock

(option 01)

1 2 3 4 5 6 7 8 9 10 ... 65 66

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